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DATA SHEET MOS FIELD EFFECT TRANSISTOR PA2712GR SWITCHING P-CHANNEL POWER MOS FET DESCRIPTION The PA2712GR is P-Channel MOS Field Effect Transistor designed for power management applications of notebook computers and Li-ion battery protection circuit. PACKAGE DRAWING (Unit: mm) 8 5 1, 2, 3 ; Source 4 ; Gate 5, 6, 7, 8 ; Drain 1.8 MAX. * Low on-state resistance RDS(on)1 = 13 m MAX. (VGS = -10 V, ID = -5.0 A) RDS(on)2 = 21 m MAX. (VGS = -4.5 V, ID = -5.0 A) RDS(on)3 = 26 m MAX. (VGS = -4.0 V, ID = -5.0 A) * Low Ciss: Ciss = 2000 pF TYP. * Small and surface mount package (Power SOP8) FEATURES 1 4 5.37 MAX. +0.10 -0.05 6.0 0.3 4.4 0.8 1.44 0.15 0.05 MIN. ORDERING INFORMATION PART NUMBER PACKAGE Power SOP8 0.5 0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 -0.05 0.12 M PA2712GR ABSOLUTE MAXIMUM RATINGS (TA = 25C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) Drain Current (pulse) Note1 Note2 Note3 VDSS VGSS ID(DC) ID(pulse) PT1 PT2 Tch Tstg -30 V V A A W W C C A mJ Source Gate Body Diode m20 m10 m40 2 2 150 -55 to +150 -10 EQUIVALENT CIRCUIT Drain Total Power Dissipation Total Power Dissipation Channel Temperature Storage Temperature Single Avalanche Current Single Avalanche Energy Notes 1. 2. 3. 4. Remark Note4 Note4 IAS EAS 10 PW 10 s, Duty Cycle 1% 2 Mounted on ceramic substrate of 1200 mm x 2.2 mm Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec Starting Tch = 25C, VDD = -15 V, RG = 25 , L = 100 H, VGS = -20 0 V Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. Document No. G15980EJ2V0DS00 (2nd edition) Date Published November 2002 NS CP(K) Printed in Japan The mark ! shows major revised points. 2002 PA2712GR ELECTRICAL CHARACTERISTICS (TA = 25C, All terminals are connected.) CHARACTERISTICS Zero Gate Voltage Drain Current Gate Leakage Current Gate Cut-off Voltage Forward Transfer Admittance Drain to Source On-state Resistance SYMBOL IDSS IGSS VGS(off) | yfs | RDS(on)1 RDS(on)2 RDS(on)3 Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr VDD = -24 V VGS = -10 V ID = 10 A IF = 10 A, VGS = 0 V IF = 10 A, VGS = 0 V di/dt = 100 A/s TEST CONDITIONS VDS = -30 V, VGS = 0 V VGS = m20 V, VDS = 0 V VDS = -10 V, ID = -1 mA VDS = -10 V, ID = -5.0 A VGS = -10 V, ID = -5.0 A VGS = -4.5 V, ID = -5.0 A VGS = -4.0 V, ID = -5.0 A VDS = -10 V VGS = 0 V f = 1 MHz VDD = -15 V, ID = -5.0 A VGS = -10 V RG = 10 -1.0 7 15 10 15 19 2000 550 340 10 16 92 51 42 6 12 0.82 46 33 13 21 26 MIN. TYP. MAX. -1 UNIT A nA V S m m m pF pF pF ns ns ns ns nC nC nC V ns nC m100 -2.5 TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 PG. VGS = -20 0 V 50 TEST CIRCUIT 2 SWITCHING TIME D.U.T. L VDD PG. RG VGS(-) RL VDD VDS(-) 90% 90% 10% 10% VGS Wave Form 0 10% VGS 90% BVDSS IAS ID VDD VDS VGS(-) 0 VDS VDS Wave Form 0 td(on) ton = 1 s Duty Cycle 1% tr td(off) toff tf Starting Tch TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = -2 mA PG. 50 RL VDD 2 Data Sheet G15980EJ2V0DS PA2712GR TYPICAL CHARACTERISTICS (TA = 25C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA dT - Percentage of Rated Power - % 120 TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 2.8 PT - Total Power Dissipation - W 100 2.4 2 1.6 1.2 0.8 0.4 0 Mounted on ceramic substrate of 2 1200 mm x 2.2 mm 80 60 40 20 0 0 25 50 75 100 125 150 175 0 25 50 75 100 125 150 175 TA - Ambient Temperature - C TA - Ambient Temperature - C FORWARD BIAS SAFE OPERATING AREA - 100 ID(pulse) ID(DC) - 10 PW = 100 s ID - Drain Current - A 1 ms RDS(on) Limited (at VGS = 10 V) -1 10 ms 100 ms Power Dissipation Limited - 0.1 TA = 25C Single Pulse Mounted on ceramic substrate of 2 1200 mm x 2.2 mm - 0.1 -1 - 10 DC - 0.01 - 0.01 - 100 VDS - Drain to Source Voltage - V 5 1000 TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(t) - Transient Thermal Resistance - C/W Rth(ch-A) = 62.5C/W 100 10 1 0.1 Single Pulse 2 Mounted on ceramic substrate of 1200 mm x 2.2 mm TA = 25C 0.01 100 1m 10 m PW - Pulse Width - s Data Sheet G15980EJ2V0DS 100 m 1 10 100 1000 3 PA2712GR DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE - 50 FORWARD TRANSFER CHARACTERISTICS - 100 ID - Drain Current - A VGS = -10 V ID - Drain Current - A - 40 -4.5 V -4.0 V - 10 - 30 -1 - 20 Tch = -55C 25C 75C 150C - 0.1 - 10 Pulsed 0 0 - 0.2 - 0.4 - 0.6 - 0.8 -1 - 1.2 VDS = -10 V Pulsed - 0.01 0 -1 -2 -3 -4 -5 VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE -3 100 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT | yfs | - Forward Transfer Admittance - S Tch = -55C 25C 75C 150C 10 VGS(off) - Gate Cut-off Voltage - V - 2.5 -2 - 1.5 -1 1 - 0.5 VDS = -10 V ID = -1 mA 0 -50 0 50 100 150 VDS = -10 V Pulsed 0.1 - 0.1 -1 - 10 - 100 Tch - Channel Temperature - C ID - Drain Current - A RDS(on) - Drain to Source On-state Resistance - m 40 RDS(on) - Drain to Source On-state Resistance - m DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT Pulsed DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 40 Pulsed 30 30 20 VGS = -4.0 V 20 -4.5 V 10 10 ID = -5.0 A -10 V 0 0 -5 - 10 - 15 - 20 0 - 0.1 -1 - 10 - 100 ID - Drain Current - A VGS - Gate to Source Voltage - V 4 Data Sheet G15980EJ2V0DS PA2712GR DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 30 CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 10000 RDS(on) - Drain to Source On-state Resistance - m 25 VGS = -4.0 V Ciss, Coss, Crss - Capacitance - pF Ciss 1000 20 -4.5 V 15 Coss 10 -10 V Crss 100 5 ID = -5.0 A Pulsed 0 -50 0 50 100 150 VGS = 0 V f = 1 MHz 10 - 0.01 - 0.1 -1 - 10 - 100 Tch - Channel Temperature - C VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS 1000 DYNAMIC INPUT/OUTPUT CHARACTERISTICS - 30 - 15 VDS - Drain to Source Voltage - V td(off) 100 - 20 VDD = -24 V -15 V -6 V - 10 tf tr 10 VGS - 10 -5 td(on) VDD = -15 V VGS = -10 V RG = 10 1 - 0.1 -1 - 10 - 100 VDS 0 0 10 20 30 40 50 0 ID - Drain Current - A QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE 1000 1000 REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT trr - Reverse Recovery Time - ns IF - Diode Forward Current - A 100 VGS = -10 V 0V 100 10 1 10 0.1 Pulsed 0.01 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1 0.1 1 10 di/dt = 100 A/s VGS = 0 V 100 VF(S-D) - Source to Drain Voltage - V IF - Diode Forward Current - A VGS - Gate to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns Data Sheet G15980EJ2V0DS 5 PA2712GR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD - 100 100 SINGLE AVALANCHE ENERGY DERATING FACTOR VDD = -15 V RG = 25 VGS = -20 0 V IAS -10 A IAS - Single Avalanche Current - A Energy Derating Factor - % 80 IAS = -10 A - 10 EAS = 10 mJ 60 40 -1 VDD = -15 V RG = 25 VGS = -20 0 V Starting Tch = 25C 20 - 0.1 0.01 0 0.1 1 10 25 50 75 100 125 150 L - Inductive Load - mH Starting Tch - Starting Channel Temperature - C 6 Data Sheet G15980EJ2V0DS PA2712GR [MEMO] Data Sheet G15980EJ2V0DS 7 PA2712GR * The information in this document is current as of November, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11 |
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